1. Field of the Invention
The present invention relates in general to a structure and fabricating method for semiconductor memory. In particular, the present invention relates to a structure and fabricating method for split gate flash memory.
2. Description of the Related Art
A flash memory device is a non-volatile memory, derived from erasable programmable read-only memory (EPROM) and electrically-erasable programmable read-only memory (EEPROM). Flash memory is being increasingly used to store execution codes and data in portable electronic products, such as computer systems.
A typical flash memory comprises a memory array having a large number of memory cells arranged in blocks. Each of the memory cells is fabricated as a field-effect transistor having a control gate and a floating gate. The floating gate is capable of holding a charge, and is separated, by a layer of thin oxide, from source and drain regions contained in a substrate. Each of the memory cells can be electrically programmed (charged) by injecting electrons from the drain region through the oxide layer onto the floating gate. The charge can be removed from the floating gate by tunneling the electrons to the source through the oxide layer during an erase operation. Thus the data in a memory cell is determined by the presence or absence of a charge on the floating gate.
Stacked-gate and split-gate types are typically used in the memory cell structures of the flash memory.
Since the stacked-gate type memory cell structure is the same as the standard memory cell structure of the EPROM, it is advantageous for size reduction. However, there is a disadvantage in that the operational characteristics of the flash deteriorate during an erase operation due to overerase.
The split gate flash memory, in which the control gate includes a first portion overlaying a floating gate and a second portion directly overlaying the channel, is not susceptible to overerase problems. However, the size of the split gate flash memory cell is not small enough to achieve sufficiently reduced production costs.
The object of the present invention is to provide a structure and fabrication method for split gate flash memory with reduced size.
The present invention provides a method for forming a split gate flash memory. A substrate having a pad oxide layer and a pad nitride layer thereon is provided. A trench is formed in the substrate, the pad oxide layer and the pad nitride layer. First type dopants are implanted in the bottom of the trench to form a drain in the substrate. A first oxide layer is formed on the bottom and sidewall of the trench. A first polysilicon layer is formed on the sidewall of the trench to function as a floating gate. A second oxide layer is conformally formed in the trench on the first polysilicon layer and the first oxide layer. The pad nitride layer is removed to expose the pad oxide layer. The pad oxide layer is removed to expose the substrate. A third oxide layer is conformally formed. A second polysilicon layer is conformally formed on the third oxide layer. A first nitride layer is conformally formed on the second polysilicon layer. A fourth oxide layer is formed on the first nitride layer. A part of the fourth oxide layer is removed by CMP using the first nitride layer as a stop layer to expose a top, approximately horizontal surface of the first nitride layer. The first nitride layer is etched to expose a top, approximately horizontal surface of the second polysilicon layer. The other part of the fourth oxide layer is removed. A fifth oxide layer is formed on the top surface of the second polysilicon layer. The first nitride layer and the second polysilicon layer not protected by the fifth oxide layer are removed to expose the third oxide layer, thereby defining the second polysilicon layer to function as a control gate. First type dopants are implanted in the substrate to form a source outside the trench. A dielectric layer is formed on the third oxide layer, the fifth oxide layer and the control gate. A bit line is formed on the dielectric layer connecting to the drain.
The present invention provides a split gate flash memory. A drain is disposed in the bottom of a trench formed in a substrate. A source is disposed in the substrate outside the trench. A striped floating gate is disposed at a sidewall of the trench, wherein one side of the striped floating gate is near the bottom of the trench, and the other side of the striped floating gate protrudes above the substrate. A control gate winds along the floating gate, wherein one side of the control gate is near the bottom of the trench, and the other side of the control gate is outside the trench. A metal bit line connects to the drain.